As the demand for more powerful computing devices increases, more and more systems are offered that comprise more than just one processor.
For the purposes of the present invention, a distinction is to be made between computer systems that comprise two or more discrete processors and system where two or more processors are integrated on the same chip. A computer with a main central processing unit (CPU) on a mother board and an algorithmic processor on a graphics card is an example for a computer system with two discrete processors. Another example of a computer system with several discrete processors is a parallel computer where an array of processors is arranged such that an improved performance is achieved. For the sake of simplicity, systems on a board with two or more discrete processors are also considered to belong to the same category.
There are systems where two or more processors are integrated on the same chip or semiconductor die. A typical example is a SmartCard (also referred to as integrated circuit card) that has a main processor and a crypto-processor on the same semiconductor die.
As small handheld devices are becoming more and more popular, the demand for powerful and flexible chips is increasing. A typical example is the cellular phone which in the beginning of its dissemination was just a telephone for voice transmission (analog communication). Over the years additional features have been added and most of today's cellular phones are designed for voice and data services. Additional differentiators are wireless application protocol (WAP) support, paging and short message system (SMS) functionality, just to name some of the more recent developments. All these features require more powerful processors and quite often even dual-processor or multi-processor chips.
In the future, systems handling digital video streams for example will become available. These systems also require powerful and flexible chip sets.
Other examples are integrated circuit cards, such as multi-purpose JavaCards, small handheld devices, such as palm top computers or personal digital assistants (PDAs), and so forth.
It is essential for such dual-processor or multi-processor chips that there exists a communication channel for efficient inter-processor communication. The expression “inter-processor communication” is herein used as a synonym for any communication between a first processor and/or system resources associated with this first processor and a second processor and/or system resources associated with this second processor. A shared memory is an example of a system resource that needs to be accessible by all processors of a chip.
System resources have to be shared in an efficient manner in dual-processor or multi-processor chips where the processors operate in parallel on the same aspect of a task or on different aspects of the same task. The sharing of resources may also be necessary in applications where processors are called upon to process related data.
An example of a multi-processor system is given in the European Patent application EP 0580961-A1, filed on Apr. 16, 1993. The cited Patent application concerns a system with multiple discrete processors and a global bus that is shared by all these processors. Enhanced processor interfaces are provided for linking the processors to the common bus. Such multi-processor systems are not possible for RISC processors, due to the high bus load which would have an impact on the system's performance. The multi-processor system presented in EP 0 580 961-A1 is powerful but complicated and expensive to implement. The shown structure cannot be used in multi-processor systems on a common die.
Another system is proposed in U.S. Pat. No. 4,866,597, filed on Apr. 26, 1985. This US Patent concerns a multi-processor system where each processor has its own processor bus. Data are exchanged between these processors via first-in-first-out data buffers (FIFO) which directly interconnect the respective processor buses. It is a disadvantage of this approach that the size of the buffers increases dramatically with the amount of data to be transferred.
A multi-processor system with a shared memory is described and claimed in U.S. Pat. No. 5,283,903, filed on Sep. 17, 1991. The system in accordance with this US Patent comprises a plurality of processors, a shared memory (main memory), and a priority selector unit. The priority selector unit arbitrates between those processors the request access to the shared memory. This is necessary, since the shared memory is a single-port memory (e.g., a random access memory) that cannot handle simultaneous and competing requests from several processors. It is a disadvantage of this approach that the shared memory is expensive as only intermediate storage. The shared memory may become large with high data transfer.
Another multi-processor system is described in U.S. Pat. No. 5,289,588, filed on Apr. 24, 1990. The processors are coupled by a common bus. They can access a shared memory via this common bus. A cache is associated with each processor and an arbitration scheme is employed to control the access to the shared memory. It is a disadvantage of this approach that the cache memory is expensive as only big caches give a real performance boost. In addition, bus conflicts lead to a reduced performance of each processor.
A microprocessor architecture is described in the PCT Patent application PCT/JP92/00869, filed on Jul. 7, 1992, and published under PCT Publication number WO 93/01553. The architecture supports multiple heterogeneous processors which are coupled by data, address, and control signal buses. Access to a memory is controlled by arbitration circuits.
Some of the known multi-processor systems use architectures where the inter-processor communication occupies part of the processor's processing cycles. It is desirable to avoid this overhead and to free-up the processor's processing power in order to be able to exploit the processor's capabilities and performance.
Other known schemes cannot be used for integrated multi-processor systems where two or more processors are located within the same chip.
It is yet another disadvantage of some known systems that they are asymmetric in their implementation which means that different implementations are required for each processor. Furthermore, the effort for formal verification is greater for asymmetric than for symmetric implementations.